Daniel Walker
2007-08-08 00:06:49 UTC
This patch below hangs my system on boot if I set nmi_watchdog=2 . It
shows the NMI as stuck then the system hangs .. nmi_watchdog=1 works
fine, and the system boots without any watchdog options ..
The machine is an Intel allagash development board, and it has two dual
core Pentium-M cpus. I attached the .config I used.
bf8696ed6dfa561198b4736deaf11ab68dcc4845 is first bad commit
commit bf8696ed6dfa561198b4736deaf11ab68dcc4845
Author: Stephane Eranian <***@hpl.hp.com>
Date: Wed May 2 19:27:05 2007 +0200
[PATCH] i386: i386 make NMI use PERFCTR1 for architectural perfmon (take 2)
Hello,
This patch against 2.6.20-git14 makes the NMI watchdog use PERFSEL1/PERFCTR1
instead of PERFSEL0/PERFCTR0 on processors supporting Intel architectural
perfmon, such as Intel Core 2. Although all PMU events can work on
both counters, the Precise Event-Based Sampling (PEBS) requires that the
event be in PERFCTR0 to work correctly (see section 18.14.4.1 in the
IA32 SDM Vol 3b).
A similar patch for x86-64 is to follow.
Changelog:
- make the i386 NMI watchdog use PERFSEL1/PERFCTR1 instead of PERFSEL0/PERFCTR0
on processors supporting the Intel architectural perfmon (e.g. Core 2 Duo).
This allows PEBS to work when the NMI watchdog is active.
signed-off-by: stephane eranian <***@hpl.hp.com>
Signed-off-by: Andi Kleen <***@suse.de>
:040000 040000 9cee0745798cb56da2ca82032b8ee88a2c32700a f59ee02e3cd8f13503edb7312a3494f4d7ec0069 M arch
shows the NMI as stuck then the system hangs .. nmi_watchdog=1 works
fine, and the system boots without any watchdog options ..
The machine is an Intel allagash development board, and it has two dual
core Pentium-M cpus. I attached the .config I used.
bf8696ed6dfa561198b4736deaf11ab68dcc4845 is first bad commit
commit bf8696ed6dfa561198b4736deaf11ab68dcc4845
Author: Stephane Eranian <***@hpl.hp.com>
Date: Wed May 2 19:27:05 2007 +0200
[PATCH] i386: i386 make NMI use PERFCTR1 for architectural perfmon (take 2)
Hello,
This patch against 2.6.20-git14 makes the NMI watchdog use PERFSEL1/PERFCTR1
instead of PERFSEL0/PERFCTR0 on processors supporting Intel architectural
perfmon, such as Intel Core 2. Although all PMU events can work on
both counters, the Precise Event-Based Sampling (PEBS) requires that the
event be in PERFCTR0 to work correctly (see section 18.14.4.1 in the
IA32 SDM Vol 3b).
A similar patch for x86-64 is to follow.
Changelog:
- make the i386 NMI watchdog use PERFSEL1/PERFCTR1 instead of PERFSEL0/PERFCTR0
on processors supporting the Intel architectural perfmon (e.g. Core 2 Duo).
This allows PEBS to work when the NMI watchdog is active.
signed-off-by: stephane eranian <***@hpl.hp.com>
Signed-off-by: Andi Kleen <***@suse.de>
:040000 040000 9cee0745798cb56da2ca82032b8ee88a2c32700a f59ee02e3cd8f13503edb7312a3494f4d7ec0069 M arch