[PATCH RFT 0/8] Marvell PXA168 libphy handling and Berlin Ethernet

[Sebastian Hesselbarth]

This patch series deals with a removing a IP feature that can be found
on all currently supported Marvell Ethernet IP (pxa168_eth, mv643xx_eth=
,
mvneta). The MAC IP allows to automatically perform PHY auto-negotiatio=
n
without software interaction.

However, this feature (a) fundamentally clashes with the way libphy wor=
ks
and (b) is unable to deal with quirky PHYs that require special treatme=
nt.
In this series, pxa168_eth driver is rewritten to completely disable th=
at
feature and properly deal with libphy provided PHYs. The other two driv=
ers
are suspect to future patch sets, also removing the code related with i=
t.

Currently, the patches are based on next-20141009 and will be resent on=
ce
v3.18-rc1 drops. This is a Request-For-Test on both BG2Q and MMP/gplug =
as
these are the current users of pxa168_eth. A branch with this patches o=
n
top of next-20141009 can be found at

git://git.infradead.org/users/hesselba/linux-berlin.git devel/bg2-bg2cd=
-eth-v1

It would be great to get a Tested-byfrom MMP guys on gplug - if they
have that board somewhere. Also, BG2Q (Antoine) needs a phy-connection-=
type
property. My guess is that, if it is using internal PHY, it is "mii", t=
oo.

Patch 1 adds support for Marvell 88E3016 FastEthernet PHY that is also
integrated in Marvell Berlin BG2/BG2CD SoCs.

Patch 2 allows to pass phy_interface_t on pxa168_eth platform_data that
is only used by mach-mmp/gplug. From the board setup, I guessed gplug's
PHY is connected via RMII. The patch isn't even compile tested, so here
I need a Tested-by from MMP guys.

Patches 3-5 prepare proper libphy handling and finally remove all in-dr=
iver
PHY mangling related to the feature explained above.

Patches 6-8 add corresponding ethernet DT nodes to BG2, BG2CD, and
BG2-based Sony NSZ-GS7. I have tested all this on GS7 successfully with
ip=3Ddhcp on 100M FD.

Sebastian Hesselbarth (8):
phy: marvell: Add support for 88E3016 FastEthernet PHY
net: pxa168_eth: Provide phy_interface mode on platform_data
net: pxa168_eth: Prepare proper libphy handling
net: pxa168_eth: Remove HW auto-negotiaion
net: pxa168_eth: Remove in-driver PHY mangling
ARM: berlin: Add BG2 ethernet DT nodes
ARM: berlin: Add BG2CD ethernet DT nodes
ARM: berlin: Enable ethernet on Sony NSZ-GS7

arch/arm/boot/dts/berlin2-sony-nsz-gs7.dts | 2 +
arch/arm/boot/dts/berlin2.dtsi | 36 +++++
arch/arm/boot/dts/berlin2cd.dtsi | 36 +++++
arch/arm/mach-mmp/gplugd.c | 2 +
drivers/net/ethernet/marvell/pxa168_eth.c | 242 +++++++++++----------=
--------
drivers/net/phy/marvell.c | 46 ++++++
include/linux/marvell_phy.h | 1 +
include/linux/pxa168_eth.h | 1 +
8 files changed, 218 insertions(+), 148 deletions(-)

---
Cc: "David S. Miller" <davem-fT/PcQaiUtIeIZ0/***@public.gmane.org>
Cc: "Antoine T=C3=A9nart" <antoine.tenart-wi1+55ScJUtKEb57/***@public.gmane.org>
Cc: Florian Fainelli <f.fainelli-***@public.gmane.org>
Cc: Eric Miao <eric.y.miao-***@public.gmane.org>
Cc: Haojian Zhuang <haojian.zhuang-***@public.gmane.org>
Cc: linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+***@public.gmane.org
Cc: netdev-***@public.gmane.org
Cc: devicetree-***@public.gmane.org
Cc: linux-kernel-***@public.gmane.org
--=20
2.1.1

--
To unsubscribe from this list: send the line "unsubscribe devicetree" i=
n
the body of a message to majordomo-***@public.gmane.org
More majordomo info at http://vger.kernel.org/majordomo-info.html

[Sebastian Hesselbarth]

Marvell 88E3016 is a FastEthernet PHY that also can be found in Marvell
Berlin SoCs as integrated PHY.

Signed-off-by: Sebastian Hesselbarth <***@gmail.com>
---
Cc: "David S. Miller" <***@davemloft.net>
Cc: "Antoine T=C3=A9nart" <***@free-electrons.com>
Cc: Florian Fainelli <***@gmail.com>
Cc: linux-arm-***@lists.infradead.org
Cc: ***@vger.kernel.org
Cc: linux-***@vger.kernel.org
---
drivers/net/phy/marvell.c | 46 +++++++++++++++++++++++++++++++++++++=
++++++++
include/linux/marvell_phy.h | 1 +
2 files changed, 47 insertions(+)

diff --git a/drivers/net/phy/marvell.c b/drivers/net/phy/marvell.c
index bd37e45c89c0..d2b2f2f795d5 100644
--- a/drivers/net/phy/marvell.c
+++ b/drivers/net/phy/marvell.c
@@ -118,6 +118,9 @@
=20
#define MII_M1116R_CONTROL_REG_MAC 21
=20
+#define MII_88E3016_PHY_SPEC_CTRL 0x10
+#define MII_88E3016_DISABLE_SCRAMBLER 0x0200
+#define MII_88E3016_AUTO_MDIX_CROSSOVER 0x0030
=20
MODULE_DESCRIPTION("Marvell PHY driver");
MODULE_AUTHOR("Andy Fleming");
@@ -434,6 +437,25 @@ static int m88e1116r_config_init(struct phy_device=
*phydev)
return 0;
}
=20
+static int m88e3016_config_init(struct phy_device *phydev)
+{
+ int reg;
+
+ /* Enable Scrambler and Auto-Crossover */
+ reg =3D phy_read(phydev, MII_88E3016_PHY_SPEC_CTRL);
+ if (reg < 0)
+ return reg;
+
+ reg &=3D ~MII_88E3016_DISABLE_SCRAMBLER;
+ reg |=3D MII_88E3016_AUTO_MDIX_CROSSOVER;
+
+ reg =3D phy_write(phydev, MII_88E3016_PHY_SPEC_CTRL, reg);
+ if (reg < 0)
+ return reg;
+
+ return 0;
+}
+
static int m88e1111_config_init(struct phy_device *phydev)
{
int err;
@@ -770,6 +792,12 @@ static int marvell_read_status(struct phy_device *=
phydev)
return 0;
}
=20
+static int marvell_aneg_done(struct phy_device *phydev)
+{
+ int retval =3D phy_read(phydev, MII_M1011_PHY_STATUS);
+ return (retval < 0) ? retval : (retval & MII_M1011_PHY_STATUS_RESOLVE=
D);
+}
+
static int m88e1121_did_interrupt(struct phy_device *phydev)
{
int imask;
@@ -1050,6 +1078,23 @@ static struct phy_driver marvell_drivers[] =3D {
.suspend =3D &genphy_suspend,
.driver =3D { .owner =3D THIS_MODULE },
},
+ {
+ .phy_id =3D MARVELL_PHY_ID_88E3016,
+ .phy_id_mask =3D MARVELL_PHY_ID_MASK,
+ .name =3D "Marvell 88E3016",
+ .features =3D PHY_BASIC_FEATURES,
+ .flags =3D PHY_HAS_INTERRUPT,
+ .config_aneg =3D &genphy_config_aneg,
+ .config_init =3D &m88e3016_config_init,
+ .aneg_done =3D &marvell_aneg_done,
+ .read_status =3D &marvell_read_status,
+ .ack_interrupt =3D &marvell_ack_interrupt,
+ .config_intr =3D &marvell_config_intr,
+ .did_interrupt =3D &m88e1121_did_interrupt,
+ .resume =3D &genphy_resume,
+ .suspend =3D &genphy_suspend,
+ .driver =3D { .owner =3D THIS_MODULE },
+ },
};
=20
static int __init marvell_init(void)
@@ -1079,6 +1124,7 @@ static struct mdio_device_id __maybe_unused marve=
ll_tbl[] =3D {
{ MARVELL_PHY_ID_88E1318S, MARVELL_PHY_ID_MASK },
{ MARVELL_PHY_ID_88E1116R, MARVELL_PHY_ID_MASK },
{ MARVELL_PHY_ID_88E1510, MARVELL_PHY_ID_MASK },
+ { MARVELL_PHY_ID_88E3016, MARVELL_PHY_ID_MASK },
{ }
};
=20
diff --git a/include/linux/marvell_phy.h b/include/linux/marvell_phy.h
index 8e9a029e093d..e6982ac3200d 100644
--- a/include/linux/marvell_phy.h
+++ b/include/linux/marvell_phy.h
@@ -16,6 +16,7 @@
#define MARVELL_PHY_ID_88E1318S 0x01410e90
#define MARVELL_PHY_ID_88E1116R 0x01410e40
#define MARVELL_PHY_ID_88E1510 0x01410dd0
+#define MARVELL_PHY_ID_88E3016 0x01410e60
=20
/* struct phy_device dev_flags definitions */
#define MARVELL_PHY_M1145_FLAGS_RESISTANCE 0x00000001
--=20
2.1.1

[Sebastian Hesselbarth]

Marvell Ethernet IP supports PHY negotiation driven by HW. This
fundamentally clashes with libphy (software) driven negotiation and
also cannot cope with quirky PHYs. Therefore, always disable any HW
negotiation features and properly use libphy's phy_device.

Signed-off-by: Sebastian Hesselbarth <***@gmail.com>
---
Cc: "David S. Miller" <***@davemloft.net>
Cc: "Antoine T=C3=A9nart" <***@free-electrons.com>
Cc: Florian Fainelli <***@gmail.com>
Cc: Eric Miao <***@gmail.com>
Cc: Haojian Zhuang <***@gmail.com>
Cc: linux-arm-***@lists.infradead.org
Cc: ***@vger.kernel.org
Cc: linux-***@vger.kernel.org
---
drivers/net/ethernet/marvell/pxa168_eth.c | 94 +++++++++++++++++++++++=
+++-----
1 file changed, 79 insertions(+), 15 deletions(-)

diff --git a/drivers/net/ethernet/marvell/pxa168_eth.c b/drivers/net/et=
hernet/marvell/pxa168_eth.c
index 332700144d81..a406a91812c5 100644
--- a/drivers/net/ethernet/marvell/pxa168_eth.c
+++ b/drivers/net/ethernet/marvell/pxa168_eth.c
@@ -106,6 +106,7 @@
#define SDMA_CMD_ERD (1 << 7)
=20
/* Bit definitions of the Port Config Reg */
+#define PCR_DUPLEX_FULL (1 << 15)
#define PCR_HS (1 << 12)
#define PCR_EN (1 << 7)
#define PCR_PM (1 << 0)
@@ -113,11 +114,17 @@
/* Bit definitions of the Port Config Extend Reg */
#define PCXR_2BSM (1 << 28)
#define PCXR_DSCP_EN (1 << 21)
+#define PCXR_RMII_EN (1 << 20)
+#define PCXR_AN_SPEED_DIS (1 << 19)
+#define PCXR_SPEED_100 (1 << 18)
#define PCXR_MFL_1518 (0 << 14)
#define PCXR_MFL_1536 (1 << 14)
#define PCXR_MFL_2048 (2 << 14)
#define PCXR_MFL_64K (3 << 14)
+#define PCXR_FLOWCTL_DIS (1 << 12)
#define PCXR_FLP (1 << 11)
+#define PCXR_AN_FLOWCTL_DIS (1 << 10)
+#define PCXR_AN_DUPLEX_DIS (1 << 9)
#define PCXR_PRIO_TX_OFF 3
#define PCXR_TX_HIGH_PRI (7 << PCXR_PRIO_TX_OFF)
=20
@@ -272,6 +279,7 @@ enum hash_table_entry {
static int pxa168_get_settings(struct net_device *dev, struct ethtool_=
cmd *cmd);
static int pxa168_set_settings(struct net_device *dev, struct ethtool_=
cmd *cmd);
static int pxa168_init_hw(struct pxa168_eth_private *pep);
+static int pxa168_init_phy(struct net_device *dev);
static void eth_port_reset(struct net_device *dev);
static void eth_port_start(struct net_device *dev);
static int pxa168_eth_open(struct net_device *dev);
@@ -658,14 +666,7 @@ static void eth_port_start(struct net_device *dev)
struct pxa168_eth_private *pep =3D netdev_priv(dev);
int tx_curr_desc, rx_curr_desc;
=20
- /* Perform PHY reset, if there is a PHY. */
- if (pep->phy !=3D NULL) {
- struct ethtool_cmd cmd;
-
- pxa168_get_settings(pep->dev, &cmd);
- phy_init_hw(pep->phy);
- pxa168_set_settings(pep->dev, &cmd);
- }
+ phy_start(pep->phy);
=20
/* Assignment of Tx CTRP of given queue */
tx_curr_desc =3D pep->tx_curr_desc_q;
@@ -720,6 +721,8 @@ static void eth_port_reset(struct net_device *dev)
val =3D rdl(pep, PORT_CONFIG);
val &=3D ~PCR_EN;
wrl(pep, PORT_CONFIG, val);
+
+ phy_stop(pep->phy);
}
=20
/*
@@ -981,8 +984,11 @@ static int set_port_config_ext(struct pxa168_eth_p=
rivate *pep)
skb_size =3D PCXR_MFL_64K;
=20
/* Extended Port Configuration */
- wrl(pep,
- PORT_CONFIG_EXT, PCXR_2BSM | /* Two byte prefix aligns IP hdr */
+ wrl(pep, PORT_CONFIG_EXT,
+ PCXR_AN_SPEED_DIS | /* Disable HW AN */
+ PCXR_AN_DUPLEX_DIS |
+ PCXR_AN_FLOWCTL_DIS |
+ PCXR_2BSM | /* Two byte prefix aligns IP hdr */
PCXR_DSCP_EN | /* Enable DSCP in IP */
skb_size | PCXR_FLP | /* do not force link pass */
PCXR_TX_HIGH_PRI); /* Transmit - high priority queue */
@@ -990,6 +996,63 @@ static int set_port_config_ext(struct pxa168_eth_p=
rivate *pep)
return 0;
}
=20
+static void pxa168_eth_adjust_link(struct net_device *dev)
+{
+ struct pxa168_eth_private *pep =3D netdev_priv(dev);
+ struct phy_device *phy =3D pep->phy;
+ u32 cfg =3D rdl(pep, PORT_CONFIG);
+ u32 cfgext =3D rdl(pep, PORT_CONFIG_EXT);
+
+ cfg &=3D ~PCR_DUPLEX_FULL;
+ cfgext &=3D ~(PCXR_SPEED_100 | PCXR_FLOWCTL_DIS | PCXR_RMII_EN);
+
+ if (phy->interface =3D=3D PHY_INTERFACE_MODE_RMII)
+ cfgext |=3D PCXR_RMII_EN;
+ if (phy->speed =3D=3D SPEED_100)
+ cfgext |=3D PCXR_SPEED_100;
+ if (phy->duplex)
+ cfg |=3D PCR_DUPLEX_FULL;
+ if (!phy->pause)
+ cfgext |=3D PCXR_FLOWCTL_DIS;
+
+ wrl(pep, PORT_CONFIG, cfg);
+ wrl(pep, PORT_CONFIG_EXT, cfgext);
+}
+
+static int pxa168_init_phy(struct net_device *dev)
+{
+ struct pxa168_eth_private *pep =3D netdev_priv(dev);
+ struct ethtool_cmd cmd;
+ int err;
+
+ if (pep->phy)
+ return 0;
+
+ pep->phy =3D mdiobus_scan(pep->smi_bus, pep->phy_addr);
+ if (!pep->phy)
+ return -ENODEV;
+
+ err =3D phy_connect_direct(dev, pep->phy, pxa168_eth_adjust_link,
+ pep->phy_intf);
+ if (err)
+ return err;
+
+ err =3D pxa168_get_settings(dev, &cmd);
+ if (err)
+ return err;
+
+ cmd.phy_address =3D pep->phy_addr;
+ cmd.speed =3D pep->phy_speed;
+ cmd.duplex =3D pep->phy_duplex;
+ cmd.advertising =3D PHY_BASIC_FEATURES;
+ cmd.autoneg =3D AUTONEG_ENABLE;
+
+ if (cmd.speed !=3D 0)
+ cmd.autoneg =3D AUTONEG_DISABLE;
+
+ return pxa168_set_settings(dev, &cmd);
+}
+
static int pxa168_init_hw(struct pxa168_eth_private *pep)
{
int err =3D 0;
@@ -1136,6 +1199,10 @@ static int pxa168_eth_open(struct net_device *de=
v)
struct pxa168_eth_private *pep =3D netdev_priv(dev);
int err;
=20
+ err =3D pxa168_init_phy(dev);
+ if (err)
+ return err;
+
err =3D request_irq(dev->irq, pxa168_eth_int_handler, 0, dev->name, d=
ev);
if (err) {
dev_err(&dev->dev, "can't assign irq\n");
@@ -1596,9 +1663,6 @@ static int pxa168_eth_probe(struct platform_devic=
e *pdev)
goto err_free_mdio;
=20
pxa168_init_hw(pep);
- err =3D ethernet_phy_setup(dev);
- if (err)
- goto err_mdiobus;
SET_NETDEV_DEV(dev, &pdev->dev);
err =3D register_netdev(dev);
if (err)
@@ -1629,13 +1693,13 @@ static int pxa168_eth_remove(struct platform_de=
vice *pdev)
pep->htpr, pep->htpr_dma);
pep->htpr =3D NULL;
}
+ if (pep->phy)
+ phy_disconnect(pep->phy);
if (pep->clk) {
clk_disable(pep->clk);
clk_put(pep->clk);
pep->clk =3D NULL;
}
- if (pep->phy !=3D NULL)
- phy_detach(pep->phy);
=20
iounmap(pep->base);
pep->base =3D NULL;
--=20
2.1.1

[Sebastian Hesselbarth]

With properly using libphy PHYs now, remove the in-driver PHY
mangling.

Signed-off-by: Sebastian Hesselbarth <***@gmail.com>
---
Cc: "David S. Miller" <***@davemloft.net>
Cc: "Antoine T=C3=A9nart" <***@free-electrons.com>
Cc: Florian Fainelli <***@gmail.com>
Cc: Eric Miao <***@gmail.com>
Cc: Haojian Zhuang <***@gmail.com>
Cc: linux-arm-***@lists.infradead.org
Cc: ***@vger.kernel.org
Cc: linux-***@vger.kernel.org
---
drivers/net/ethernet/marvell/pxa168_eth.c | 126 ----------------------=
--------
1 file changed, 126 deletions(-)

diff --git a/drivers/net/ethernet/marvell/pxa168_eth.c b/drivers/net/et=
hernet/marvell/pxa168_eth.c
index a406a91812c5..4e77c5142544 100644
--- a/drivers/net/ethernet/marvell/pxa168_eth.c
+++ b/drivers/net/ethernet/marvell/pxa168_eth.c
@@ -177,7 +177,6 @@
#define LINK_UP (1 << 3)
=20
/* Bit definitions for work to be done */
-#define WORK_LINK (1 << 0)
#define WORK_TX_DONE (1 << 1)
=20
/*
@@ -284,7 +283,6 @@ static void eth_port_reset(struct net_device *dev);
static void eth_port_start(struct net_device *dev);
static int pxa168_eth_open(struct net_device *dev);
static int pxa168_eth_stop(struct net_device *dev);
-static int ethernet_phy_setup(struct net_device *dev);
=20
static inline u32 rdl(struct pxa168_eth_private *pep, int offset)
{
@@ -316,26 +314,6 @@ static void abort_dma(struct pxa168_eth_private *p=
ep)
netdev_err(pep->dev, "%s : DMA Stuck\n", __func__);
}
=20
-static int ethernet_phy_get(struct pxa168_eth_private *pep)
-{
- unsigned int reg_data;
-
- reg_data =3D rdl(pep, PHY_ADDRESS);
-
- return (reg_data >> (5 * pep->port_num)) & 0x1f;
-}
-
-static void ethernet_phy_set_addr(struct pxa168_eth_private *pep, int =
phy_addr)
-{
- u32 reg_data;
- int addr_shift =3D 5 * pep->port_num;
-
- reg_data =3D rdl(pep, PHY_ADDRESS);
- reg_data &=3D ~(0x1f << addr_shift);
- reg_data |=3D (phy_addr & 0x1f) << addr_shift;
- wrl(pep, PHY_ADDRESS, reg_data);
-}
-
static void rxq_refill(struct net_device *dev)
{
struct pxa168_eth_private *pep =3D netdev_priv(dev);
@@ -890,43 +868,9 @@ static int pxa168_eth_collect_events(struct pxa168=
_eth_private *pep,
}
if (icr & ICR_RXBUF)
ret =3D 1;
- if (icr & ICR_MII_CH) {
- pep->work_todo |=3D WORK_LINK;
- ret =3D 1;
- }
return ret;
}
=20
-static void handle_link_event(struct pxa168_eth_private *pep)
-{
- struct net_device *dev =3D pep->dev;
- u32 port_status;
- int speed;
- int duplex;
- int fc;
-
- port_status =3D rdl(pep, PORT_STATUS);
- if (!(port_status & LINK_UP)) {
- if (netif_carrier_ok(dev)) {
- netdev_info(dev, "link down\n");
- netif_carrier_off(dev);
- txq_reclaim(dev, 1);
- }
- return;
- }
- if (port_status & PORT_SPEED_100)
- speed =3D 100;
- else
- speed =3D 10;
-
- duplex =3D (port_status & FULL_DUPLEX) ? 1 : 0;
- fc =3D (port_status & FLOW_CONTROL_DISABLED) ? 0 : 1;
- netdev_info(dev, "link up, %d Mb/s, %s duplex, flow control %sabled\n=
",
- speed, duplex ? "full" : "half", fc ? "en" : "dis");
- if (!netif_carrier_ok(dev))
- netif_carrier_on(dev);
-}
-
static irqreturn_t pxa168_eth_int_handler(int irq, void *dev_id)
{
struct net_device *dev =3D (struct net_device *)dev_id;
@@ -1301,10 +1245,6 @@ static int pxa168_rx_poll(struct napi_struct *na=
pi, int budget)
struct net_device *dev =3D pep->dev;
int work_done =3D 0;
=20
- if (unlikely(pep->work_todo & WORK_LINK)) {
- pep->work_todo &=3D ~(WORK_LINK);
- handle_link_event(pep);
- }
/*
* We call txq_reclaim every time since in NAPI interupts are disable=
d
* and due to this we miss the TX_DONE interrupt,which is not updated=
in
@@ -1427,72 +1367,6 @@ static int pxa168_eth_do_ioctl(struct net_device=
*dev, struct ifreq *ifr,
return -EOPNOTSUPP;
}
=20
-static struct phy_device *phy_scan(struct pxa168_eth_private *pep, int=
phy_addr)
-{
- struct mii_bus *bus =3D pep->smi_bus;
- struct phy_device *phydev;
- int start;
- int num;
- int i;
-
- if (phy_addr =3D=3D PXA168_ETH_PHY_ADDR_DEFAULT) {
- /* Scan entire range */
- start =3D ethernet_phy_get(pep);
- num =3D 32;
- } else {
- /* Use phy addr specific to platform */
- start =3D phy_addr & 0x1f;
- num =3D 1;
- }
- phydev =3D NULL;
- for (i =3D 0; i < num; i++) {
- int addr =3D (start + i) & 0x1f;
- if (bus->phy_map[addr] =3D=3D NULL)
- mdiobus_scan(bus, addr);
-
- if (phydev =3D=3D NULL) {
- phydev =3D bus->phy_map[addr];
- if (phydev !=3D NULL)
- ethernet_phy_set_addr(pep, addr);
- }
- }
-
- return phydev;
-}
-
-static void phy_init(struct pxa168_eth_private *pep)
-{
- struct phy_device *phy =3D pep->phy;
-
- phy_attach(pep->dev, dev_name(&phy->dev), pep->phy_intf);
-
- phy->speed =3D pep->phy_speed;
- phy->duplex =3D pep->phy_duplex;
- phy->autoneg =3D AUTONEG_ENABLE;
- phy->supported &=3D PHY_BASIC_FEATURES;
- phy->advertising =3D phy->supported | ADVERTISED_Autoneg;
-
- if (pep->phy_speed !=3D 0) {
- phy->autoneg =3D AUTONEG_DISABLE;
- phy->advertising =3D 0;
- }
-
- phy_start_aneg(phy);
-}
-
-static int ethernet_phy_setup(struct net_device *dev)
-{
- struct pxa168_eth_private *pep =3D netdev_priv(dev);
-
- pep->phy =3D phy_scan(pep, pep->phy_addr & 0x1f);
- if (pep->phy !=3D NULL)
- phy_init(pep);
-
- update_hash_table_mac_address(pep, NULL, dev->dev_addr);
-
- return 0;
-}
-
static int pxa168_get_settings(struct net_device *dev, struct ethtool_=
cmd *cmd)
{
struct pxa168_eth_private *pep =3D netdev_priv(dev);
--=20
2.1.1

[Sebastian Hesselbarth]

Marvell BG2 has two fast ethernet controllers with internal PHY,
add the corresponding nodes to SoC dtsi.

Signed-off-by: Sebastian Hesselbarth <***@gmail.com>
---
Cc: "David S. Miller" <***@davemloft.net>
Cc: "Antoine Ténart" <***@free-electrons.com>
Cc: Florian Fainelli <***@gmail.com>
Cc: Eric Miao <***@gmail.com>
Cc: Haojian Zhuang <***@gmail.com>
Cc: linux-arm-***@lists.infradead.org
Cc: ***@vger.kernel.org
Cc: ***@vger.kernel.org
Cc: linux-***@vger.kernel.org
---
arch/arm/boot/dts/berlin2.dtsi | 36 ++++++++++++++++++++++++++++++++++++
1 file changed, 36 insertions(+)

diff --git a/arch/arm/boot/dts/berlin2.dtsi b/arch/arm/boot/dts/berlin2.dtsi
index d7e81e124de0..5f82dcfc6ac6 100644
--- a/arch/arm/boot/dts/berlin2.dtsi
+++ b/arch/arm/boot/dts/berlin2.dtsi
@@ -79,11 +79,47 @@
clocks = <&chip CLKID_TWD>;
};

+ eth1: ***@b90000 {
+ compatible = "marvell,pxa168-eth";
+ reg = <0xb90000 0x10000>;
+ clocks = <&chip CLKID_GETH1>;
+ interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
+ /* set by bootloader */
+ local-mac-address = [00 00 00 00 00 00];
+ #address-cells = <1>;
+ #size-cells = <0>;
+ phy-handle = <&ethphy1>;
+ status = "disabled";
+
+ ethphy1: ethernet-***@0 {
+ phy-connection-type = "mii";
+ reg = <0>;
+ };
+ };
+
cpu-***@dd0000 {
compatible = "marvell,berlin-cpu-ctrl";
reg = <0xdd0000 0x10000>;
};

+ eth0: ***@e50000 {
+ compatible = "marvell,pxa168-eth";
+ reg = <0xe50000 0x10000>;
+ clocks = <&chip CLKID_GETH0>;
+ interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
+ /* set by bootloader */
+ local-mac-address = [00 00 00 00 00 00];
+ #address-cells = <1>;
+ #size-cells = <0>;
+ phy-handle = <&ethphy0>;
+ status = "disabled";
+
+ ethphy0: ethernet-***@0 {
+ phy-connection-type = "mii";
+ reg = <0>;
+ };
+ };
+
***@e80000 {
compatible = "simple-bus";
#address-cells = <1>;

[Sebastian Hesselbarth]

Marvell Berlin BG2 based Sony NSZ-GS7 has one ethernet controller
connected to rear RJ45 jack. Enable it by default.

Signed-off-by: Sebastian Hesselbarth <***@gmail.com>
---
Cc: "David S. Miller" <***@davemloft.net>
Cc: "Antoine T=C3=A9nart" <***@free-electrons.com>
Cc: Florian Fainelli <***@gmail.com>
Cc: Eric Miao <***@gmail.com>
Cc: Haojian Zhuang <***@gmail.com>
Cc: linux-arm-***@lists.infradead.org
Cc: ***@vger.kernel.org
Cc: ***@vger.kernel.org
Cc: linux-***@vger.kernel.org
---
arch/arm/boot/dts/berlin2-sony-nsz-gs7.dts | 2 ++
1 file changed, 2 insertions(+)

diff --git a/arch/arm/boot/dts/berlin2-sony-nsz-gs7.dts b/arch/arm/boot=
/dts/berlin2-sony-nsz-gs7.dts
index c72bfd468d10..27f2f0ad7562 100644
--- a/arch/arm/boot/dts/berlin2-sony-nsz-gs7.dts
+++ b/arch/arm/boot/dts/berlin2-sony-nsz-gs7.dts
@@ -26,4 +26,6 @@
};
};
=20
+&eth1 { status =3D "okay"; };
+
&uart0 { status =3D "okay"; };
--=20
2.1.1

[Sebastian Hesselbarth]

Marvell BG2CD has two fast ethernet controllers with internal PHY,
add the corresponding nodes to SoC dtsi.

Signed-off-by: Sebastian Hesselbarth <***@gmail.com>
---
Cc: "David S. Miller" <***@davemloft.net>
Cc: "Antoine T=C3=A9nart" <***@free-electrons.com>
Cc: Florian Fainelli <***@gmail.com>
Cc: Eric Miao <***@gmail.com>
Cc: Haojian Zhuang <***@gmail.com>
Cc: linux-arm-***@lists.infradead.org
Cc: ***@vger.kernel.org
Cc: ***@vger.kernel.org
Cc: linux-***@vger.kernel.org
---
arch/arm/boot/dts/berlin2cd.dtsi | 36 ++++++++++++++++++++++++++++++++=
++++
1 file changed, 36 insertions(+)

diff --git a/arch/arm/boot/dts/berlin2cd.dtsi b/arch/arm/boot/dts/berli=
n2cd.dtsi
index 68f7032b4686..ee3a22ad4b5f 100644
--- a/arch/arm/boot/dts/berlin2cd.dtsi
+++ b/arch/arm/boot/dts/berlin2cd.dtsi
@@ -66,6 +66,42 @@
clocks =3D <&chip CLKID_TWD>;
};
=20
+ eth1: ***@b90000 {
+ compatible =3D "marvell,pxa168-eth";
+ reg =3D <0xb90000 0x10000>;
+ clocks =3D <&chip CLKID_GETH1>;
+ interrupts =3D <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
+ /* set by bootloader */
+ local-mac-address =3D [00 00 00 00 00 00];
+ #address-cells =3D <1>;
+ #size-cells =3D <0>;
+ phy-handle =3D <&ethphy1>;
+ status =3D "disabled";
+
+ ethphy1: ethernet-***@0 {
+ phy-connection-type =3D "mii";
+ reg =3D <0>;
+ };
+ };
+
+ eth0: ***@e50000 {
+ compatible =3D "marvell,pxa168-eth";
+ reg =3D <0xe50000 0x10000>;
+ clocks =3D <&chip CLKID_GETH0>;
+ interrupts =3D <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
+ /* set by bootloader */
+ local-mac-address =3D [00 00 00 00 00 00];
+ #address-cells =3D <1>;
+ #size-cells =3D <0>;
+ phy-handle =3D <&ethphy0>;
+ status =3D "disabled";
+
+ ethphy0: ethernet-***@0 {
+ phy-connection-type =3D "mii";
+ reg =3D <0>;
+ };
+ };
+
***@e80000 {
compatible =3D "simple-bus";
#address-cells =3D <1>;
--=20
2.1.1

[Sebastian Hesselbarth]

Current libphy handling in pxa168_eth lacks proper phy_connect. Prepare
to fix this by first moving phy properties from platform_data to private
driver data.

Signed-off-by: Sebastian Hesselbarth <***@gmail.com>
---
Cc: "David S. Miller" <***@davemloft.net>
Cc: "Antoine Ténart" <***@free-electrons.com>
Cc: Florian Fainelli <***@gmail.com>
Cc: Eric Miao <***@gmail.com>
Cc: Haojian Zhuang <***@gmail.com>
Cc: linux-arm-***@lists.infradead.org
Cc: ***@vger.kernel.org
Cc: linux-***@vger.kernel.org
---
drivers/net/ethernet/marvell/pxa168_eth.c | 38 +++++++++++++++++++------------
1 file changed, 23 insertions(+), 15 deletions(-)

diff --git a/drivers/net/ethernet/marvell/pxa168_eth.c b/drivers/net/ethernet/marvell/pxa168_eth.c
index c3b209cd0660..332700144d81 100644
--- a/drivers/net/ethernet/marvell/pxa168_eth.c
+++ b/drivers/net/ethernet/marvell/pxa168_eth.c
@@ -197,6 +197,9 @@ struct tx_desc {
struct pxa168_eth_private {
int port_num; /* User Ethernet port number */
int phy_addr;
+ int phy_speed;
+ int phy_duplex;
+ phy_interface_t phy_intf;

int rx_resource_err; /* Rx ring resource error flag */

@@ -1394,19 +1397,17 @@ static void phy_init(struct pxa168_eth_private *pep)
{
struct phy_device *phy = pep->phy;

- phy_attach(pep->dev, dev_name(&phy->dev), PHY_INTERFACE_MODE_MII);
+ phy_attach(pep->dev, dev_name(&phy->dev), pep->phy_intf);

- if (pep->pd && pep->pd->speed != 0) {
+ phy->speed = pep->phy_speed;
+ phy->duplex = pep->phy_duplex;
+ phy->autoneg = AUTONEG_ENABLE;
+ phy->supported &= PHY_BASIC_FEATURES;
+ phy->advertising = phy->supported | ADVERTISED_Autoneg;
+
+ if (pep->phy_speed != 0) {
phy->autoneg = AUTONEG_DISABLE;
phy->advertising = 0;
- phy->speed = pep->pd->speed;
- phy->duplex = pep->pd->duplex;
- } else {
- phy->autoneg = AUTONEG_ENABLE;
- phy->speed = 0;
- phy->duplex = 0;
- phy->supported &= PHY_BASIC_FEATURES;
- phy->advertising = phy->supported | ADVERTISED_Autoneg;
}

phy_start_aneg(phy);
@@ -1416,9 +1417,6 @@ static int ethernet_phy_setup(struct net_device *dev)
{
struct pxa168_eth_private *pep = netdev_priv(dev);

- if (pep->pd && pep->pd->init)
- pep->pd->init();
-
pep->phy = phy_scan(pep, pep->phy_addr & 0x1f);
if (pep->phy != NULL)
phy_init(pep);
@@ -1552,13 +1550,23 @@ static int pxa168_eth_probe(struct platform_device *pdev)

pep->port_num = pep->pd->port_number;
pep->phy_addr = pep->pd->phy_addr;
+ pep->phy_speed = pep->pd->speed;
+ pep->phy_duplex = pep->pd->duplex;
+ pep->phy_intf = pep->pd->intf;
+
+ if (pep->pd->init)
+ pep->pd->init();
} else if (pdev->dev.of_node) {
of_property_read_u32(pdev->dev.of_node, "port-id",
&pep->port_num);

np = of_parse_phandle(pdev->dev.of_node, "phy-handle", 0);
- if (np)
- of_property_read_u32(np, "reg", &pep->phy_addr);
+ if (!np) {
+ dev_err(&pdev->dev, "missing phy-handle\n");
+ return -EINVAL;
+ }
+ of_property_read_u32(np, "reg", &pep->phy_addr);
+ pep->phy_intf = of_get_phy_mode(np);
}

/* Hardware supports only 3 ports */

[Sebastian Hesselbarth]

The PXA168 Ethernet IP support MII and RMII connection to its PHY.
Currently, pxa168 platform_data does not provide a way to pass that
and there is one user of pxa168 platform_data (mach-mmp/gplug).
Given the pinctrl settings of gplug it uses RMII, so add and pass
a corresponding phy_interface_t.

Signed-off-by: Sebastian Hesselbarth <***@gmail.com>
---
Cc: "David S. Miller" <***@davemloft.net>
Cc: "Antoine Ténart" <***@free-electrons.com>
Cc: Florian Fainelli <***@gmail.com>
Cc: Eric Miao <***@gmail.com>
Cc: Haojian Zhuang <***@gmail.com>
Cc: linux-arm-***@lists.infradead.org
Cc: ***@vger.kernel.org
Cc: linux-***@vger.kernel.org
---
arch/arm/mach-mmp/gplugd.c | 2 ++
include/linux/pxa168_eth.h | 1 +
2 files changed, 3 insertions(+)

diff --git a/arch/arm/mach-mmp/gplugd.c b/arch/arm/mach-mmp/gplugd.c
index d81b2475e67e..3b5794cd0357 100644
--- a/arch/arm/mach-mmp/gplugd.c
+++ b/arch/arm/mach-mmp/gplugd.c
@@ -12,6 +12,7 @@
#include <linux/platform_device.h>
#include <linux/gpio.h>
#include <linux/gpio-pxa.h>
+#include <linux/phy.h>

#include <asm/mach/arch.h>
#include <asm/mach-types.h>
@@ -158,6 +159,7 @@ struct pxa168_eth_platform_data gplugd_eth_platform_data = {
.port_number = 0,
.phy_addr = 0,
.speed = 0, /* Autonagotiation */
+ .intf = PHY_INTERFACE_MODE_RMII,
.init = gplugd_eth_init,
};

diff --git a/include/linux/pxa168_eth.h b/include/linux/pxa168_eth.h
index 18d75e795606..37c381120bc8 100644
--- a/include/linux/pxa168_eth.h
+++ b/include/linux/pxa168_eth.h
@@ -13,6 +13,7 @@ struct pxa168_eth_platform_data {
*/
int speed; /* 0, SPEED_10, SPEED_100 */
int duplex; /* DUPLEX_HALF or DUPLEX_FULL */
+ phy_interface_t intf;

/*
* Override default RX/TX queue sizes if nonzero.

[Thomas Petazzoni]

Dear Sebastian Hesselbarth,

Post by Sebastian Hesselbarth
This patch series deals with a removing a IP feature that can be found
on all currently supported Marvell Ethernet IP (pxa168_eth, mv643xx_eth,
mvneta). The MAC IP allows to automatically perform PHY auto-negotiation
without software interaction.
However, this feature (a) fundamentally clashes with the way libphy works
and (b) is unable to deal with quirky PHYs that require special treatment.
In this series, pxa168_eth driver is rewritten to completely disable that
feature and properly deal with libphy provided PHYs. The other two drivers
are suspect to future patch sets, also removing the code related with it.

Hum, in mvneta, we already disabled the automatic negotiation and use
libphy. What makes you think the current mvneta driver is wrong in this
respect?

Thanks,

Thomas

[Sebastian Hesselbarth]

Post by Thomas Petazzoni
Dear Sebastian Hesselbarth,

Post by Sebastian Hesselbarth
This patch series deals with a removing a IP feature that can be found
on all currently supported Marvell Ethernet IP (pxa168_eth, mv643xx_eth,
mvneta). The MAC IP allows to automatically perform PHY auto-negotiation
without software interaction.
However, this feature (a) fundamentally clashes with the way libphy works
and (b) is unable to deal with quirky PHYs that require special treatment.
In this series, pxa168_eth driver is rewritten to completely disable that
feature and properly deal with libphy provided PHYs. The other two drivers
are suspect to future patch sets, also removing the code related with it.

Hum, in mvneta, we already disabled the automatic negotiation and use
libphy. What makes you think the current mvneta driver is wrong in this
respect?

I didn't check mvneta, but remember Ezequiel didn't clear all AN bits
in the barebox driver (which is based on Linux mvneta). Just mentioned
that I'll have a closer look at it.

But I agree, regarding libphy support mvneta is probably the best
already.

Sebastian

[Thomas Petazzoni]

Dear Sebastian Hesselbarth,

Post by Sebastian Hesselbarth

Post by Thomas Petazzoni
Hum, in mvneta, we already disabled the automatic negotiation and use
libphy. What makes you think the current mvneta driver is wrong in this
respect?

I didn't check mvneta, but remember Ezequiel didn't clear all AN bits
in the barebox driver (which is based on Linux mvneta). Just mentioned
that I'll have a closer look at it.

Ah, ok.

Post by Sebastian Hesselbarth
But I agree, regarding libphy support mvneta is probably the best
already.

Well, I initially remember that the original driver coming from Marvell
was using the HW PHY stuff, and that I changed that because it would
not integrate well with the kernel libphy.

A drawback of this is that because the hardware has built-in PHY
polling which triggers a MAC interrupt when the PHY status changes, they
typically don't wire up the PHY interrupt. Therefore, since we're not
able to use the MAC interrupt for PHY event notifications, we rely on
software PHY polling, which means that link up / link down events take
a few seconds to be noticed by the kernel. Unfortunately, I don't think
the hardware allows to use the hardware PHY polling to get link changes
interrupt, but not let the hardware configure the PHY itself.

Best regards,

Thomas

[Sebastian Hesselbarth]

Post by Thomas Petazzoni
Well, I initially remember that the original driver coming from Marvell
was using the HW PHY stuff, and that I changed that because it would
not integrate well with the kernel libphy.
A drawback of this is that because the hardware has built-in PHY
polling which triggers a MAC interrupt when the PHY status changes, they
typically don't wire up the PHY interrupt. Therefore, since we're not
able to use the MAC interrupt for PHY event notifications, we rely on
software PHY polling, which means that link up / link down events take
a few seconds to be noticed by the kernel. Unfortunately, I don't think
the hardware allows to use the hardware PHY polling to get link changes
interrupt, but not let the hardware configure the PHY itself.

Yeah, but that HW PHY stuff really only works properly with standard
compliant PHYs. In particular, the integrated Marvell PHY in Marvell
Berlin SoCs does not seem to reflect PHY status on BMCR properly /sigh/.
Anyway, I think we can live with PHY polling.

BTW, one thing I noticed here is that libphy calls adjust_link
over-and-over again although nothing has changed. I guess we can just
add some before/after comparison in the libphy state machine and only
call adjust_link when something has changed. I'll have to look closer
at the state machine first and maybe Florian can comment on this,
too.

Sebastian

[Florian Fainelli]

Post by Sebastian Hesselbarth

Post by Thomas Petazzoni
Well, I initially remember that the original driver coming from Marvell
was using the HW PHY stuff, and that I changed that because it would
not integrate well with the kernel libphy.
A drawback of this is that because the hardware has built-in PHY
polling which triggers a MAC interrupt when the PHY status changes, they
typically don't wire up the PHY interrupt. Therefore, since we're not
able to use the MAC interrupt for PHY event notifications, we rely on
software PHY polling, which means that link up / link down events take
a few seconds to be noticed by the kernel. Unfortunately, I don't think
the hardware allows to use the hardware PHY polling to get link changes
interrupt, but not let the hardware configure the PHY itself.

Yeah, but that HW PHY stuff really only works properly with standard
compliant PHYs. In particular, the integrated Marvell PHY in Marvell
Berlin SoCs does not seem to reflect PHY status on BMCR properly /sigh/.
Anyway, I think we can live with PHY polling.
BTW, one thing I noticed here is that libphy calls adjust_link
over-and-over again although nothing has changed. I guess we can just
add some before/after comparison in the libphy state machine and only
call adjust_link when something has changed. I'll have to look closer
at the state machine first and maybe Florian can comment on this,
too.

There's basically nothing built in the generic libphy that would try to
limit the number of times the adjust_link() callback is invoked, some
changes went in the bcmgenet driver to avoid that, I have yet to see how
much of this logic is transferable to the libphy layer.
--
Florian

[Sebastian Hesselbarth]

Post by Florian Fainelli

Post by Sebastian Hesselbarth
Yeah, but that HW PHY stuff really only works properly with standard
compliant PHYs. In particular, the integrated Marvell PHY in Marvell
Berlin SoCs does not seem to reflect PHY status on BMCR properly /sigh/.
Anyway, I think we can live with PHY polling.
BTW, one thing I noticed here is that libphy calls adjust_link
over-and-over again although nothing has changed. I guess we can just
add some before/after comparison in the libphy state machine and only
call adjust_link when something has changed. I'll have to look closer
at the state machine first and maybe Florian can comment on this,
too.

There's basically nothing built in the generic libphy that would try to
limit the number of times the adjust_link() callback is invoked, some
changes went in the bcmgenet driver to avoid that, I have yet to see how
much of this logic is transferable to the libphy layer.

Ok, thanks for the clarification. I guess for the final patch series,
I'll add a check for both registers modified in foo_adjust_link to bail
out if there is no change. That will save the two register writes per
second or so and also allow to phy_print_status() after the writels.

Sebastian

[Antoine Tenart]

Hi Sebastian,

This patch series deals with a removing a IP feature that can be foun=

d

on all currently supported Marvell Ethernet IP (pxa168_eth, mv643xx_e=

th,

mvneta). The MAC IP allows to automatically perform PHY auto-negotiat=

ion

without software interaction.
=20
However, this feature (a) fundamentally clashes with the way libphy w=

orks

and (b) is unable to deal with quirky PHYs that require special treat=

ment.

In this series, pxa168_eth driver is rewritten to completely disable =

that

feature and properly deal with libphy provided PHYs. The other two dr=

ivers

are suspect to future patch sets, also removing the code related with=

it.

=20
Currently, the patches are based on next-20141009 and will be resent =

once

v3.18-rc1 drops. This is a Request-For-Test on both BG2Q and MMP/gplu=

g as

I tested the series on a BG2Q, it worked well.

Antoine

these are the current users of pxa168_eth. A branch with this patches=

on

top of next-20141009 can be found at
=20
git://git.infradead.org/users/hesselba/linux-berlin.git devel/bg2-bg2=

cd-eth-v1

=20
It would be great to get a Tested-byfrom MMP guys on gplug - if they
have that board somewhere. Also, BG2Q (Antoine) needs a phy-connectio=

n-type

property. My guess is that, if it is using internal PHY, it is "mii",=

too.

--=20
Antoine T=E9nart, Free Electrons
Embedded Linux, Kernel and Android engineering
http://free-electrons.com

[Sebastian Hesselbarth]

Post by Antoine Tenart

Post by Sebastian Hesselbarth
This patch series deals with a removing a IP feature that can be found
on all currently supported Marvell Ethernet IP (pxa168_eth, mv643xx_eth,
mvneta). The MAC IP allows to automatically perform PHY auto-negotiation
without software interaction.
However, this feature (a) fundamentally clashes with the way libphy works
and (b) is unable to deal with quirky PHYs that require special treatment.
In this series, pxa168_eth driver is rewritten to completely disable that
feature and properly deal with libphy provided PHYs. The other two drivers
are suspect to future patch sets, also removing the code related with it.
Currently, the patches are based on next-20141009 and will be resent once
v3.18-rc1 drops. This is a Request-For-Test on both BG2Q and MMP/gplug as

I tested the series on a BG2Q, it worked well.

Antoine,

Thanks for testing! I assume you have added a phy-connection-type
property to BG2Q's ethernet node?

I doubt there will be any Tested-by from MMP guys anytime soon, so
I'll resend this with the minor remarks to be merged for 3.19.

Sebastian

[Antoine Tenart]

Sebastian,

Post by Sebastian Hesselbarth

On Thu, Oct 09, 2014 at 02:38:58PM +0200, Sebastian Hesselbarth wrot=

This patch series deals with a removing a IP feature that can be fo=

und

Post by Sebastian Hesselbarth

on all currently supported Marvell Ethernet IP (pxa168_eth, mv643xx=

_eth,

Post by Sebastian Hesselbarth

mvneta). The MAC IP allows to automatically perform PHY auto-negoti=

ation

Post by Sebastian Hesselbarth

without software interaction.
However, this feature (a) fundamentally clashes with the way libphy=

works

Post by Sebastian Hesselbarth

and (b) is unable to deal with quirky PHYs that require special tre=

atment.

Post by Sebastian Hesselbarth

In this series, pxa168_eth driver is rewritten to completely disabl=

e that

Post by Sebastian Hesselbarth

feature and properly deal with libphy provided PHYs. The other two =

drivers

Post by Sebastian Hesselbarth

are suspect to future patch sets, also removing the code related wi=

th it.

Post by Sebastian Hesselbarth

Currently, the patches are based on next-20141009 and will be resen=

t once

Post by Sebastian Hesselbarth

v3.18-rc1 drops. This is a Request-For-Test on both BG2Q and MMP/gp=

lug as

Post by Sebastian Hesselbarth

I tested the series on a BG2Q, it worked well.

=20
Thanks for testing! I assume you have added a phy-connection-type
property to BG2Q's ethernet node?

Yes, I added the following property to the ethernet-phy node:

phy-connection-type =3D "mii";

=46eel free to add this to your series, or I can also send a patch.


Antoine

--=20
Antoine T=E9nart, Free Electrons
Embedded Linux, Kernel and Android engineering
http://free-electrons.com